In traditional circuit design tools, iteration cycles of a circuit design to comply with performance specifications occur at multiple points during the design flow. As the number of devices and components included in a circuit layout increases while their size reduces, increased current densities create deleterious effects that become more difficult to predict and tackle during the iteration cycles. As a result, the number and complexity of the iteration cycles in traditional design tools rapidly increases. In addition, the results of the iteration cycles become less predictable and more sensitive to minor details in the circuit layout design. Accordingly, traditional design tools become prone to error or time-consuming, requiring constant user attention and follow up at multiple stages.
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